An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing an Efficient Field Solving Algorithm

This paper presents an exhaustive method to characterize the interconnect capacitances with taking the floating dummy-tills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-difference solver and its computational efficiency is compared with the industry-standard RAPHAEL. Furthermore, the overall flow for extracting the parasitic capacitance considering the dummy-fills at the full-chip level is discussed and the underlying assumption is testified.